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STG3684
LOW VOLTAGE 0.5 MAX DUAL SPDT SWITCH WITH BREAK BEFORE MAKE FEATURE
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HIGH SPEED: tPD = 0.3ns (TYP.) at VCC = 3.0V tPD = 0.4ns (TYP.) at VCC = 2.3V ULTRA LOW POWER DISSIPATION: ICC = 0.2A (MAX.) at TA = 85C LOW "ON" RESISTANCE VIN = 0V: RON = 0.5 (MAX. TA = 25C) at VCC = 2.7 RON = 0.8 (MAX. TA = 25C) at VCC = 2.3V RON = 3.0 (MAX. TA = 25C) at VCC = 1.8V WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 1.65V to 4.3V SINGLE SUPPLY 4.3V TOLERANT AND 1.8V COMPATIBLE THRESHOLD ON DIGITAL CONTROL INPUT at VCC = 2.3 to 3.0V LATCH-UP PERFORMANCE EXCEEDS 300mA (JESD 17) ESD PERFORM. (ANALOG CHAN. vs GND): HBM > 7KV (MIL STD 883 method 3015)
QFN
Table 1: Order Codes
PACKAGE QFN
T&R
DESCRIPTION The STG3684 is an high-speed CMOS DUAL ANALOG S.P.D.T. (Single Pole Dual Throw) SWITCH or DUAL 2:1 Multiplexer/Demultiplexer Bus Switch fabricated in silicon gate C2MOS technology. It is designed to operate from 1.65V to 4.3V, making this device ideal for portable applications. It offers very low ON-Resistance (<0.5) at VCC=3.0V. The nIN inputs are provided to control Figure 1: Pin Connection
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the switches. The switches nS1 are ON (they are connected to common Ports Dn) when the nIN input is held high and OFF (high impedance state exists between the two ports) when nIN is held low; the switches nS2 are ON (they are connected to common Ports Dn) when the nIN input is held low and OFF (high impedance state exists between the two ports) when IN is held high. Additional key features are fast switching speed, Break Before Make Delay Time and Ultra Low Power Consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. It's available in the commercial temperature range in the QFN package.
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July 2005
Rev. 4
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STG3684
Figure 2: Input Equivalent Circuit Table 2: Pin Description
QFN PIN N 1, 9 2, 10 4, 12 3, 11 5,7,8,13,15,16 6 14 SYMBOL 1IN, 2IN 1S1 to 2S1 1S2 to 2S2 D1, D2 NC GND VCC NAME AND FUNCTION Controls Independent Channels Common Channels Not Connected Ground (0V) Positive Supply Voltage
Table 3: Truth Table
IN H L
(*) High Impedance
SWITCH S1 ON OFF(*)
SWITCH S2
Table 4: Absolute Maximum Ratings
Symbol VCC VI VIC VO IIKC IIK IOK IO IOP Parameter Supply Voltage DC Input Voltage DC Control Input Voltage DC Output Voltage DC Input Diode Current (VIN < 0V) DC Output Diode Current DC Output Current DC Input Diode Current on control pin (VIN < 0V)
DC Output Current Peak (pulse at 1ms, 10% duty cycle)
ICC or IGND DC VCC or Ground Current Power Dissipation at Ta=70C (1) PD Tstg TL Storage Temperature Lead Temperature (10 sec)
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Symbol VCC VI VIC VO Top dt/dv
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. (1) Derate above 70C: by 18.5mW/C.
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Value -0.5 to 4.6 -0.5 to 4.6 - 50 50 20 300 500 100 1120 -65 to 150 300
-0.5 to VCC + 0.5 -0.5 to VCC + 0.5
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Unit V V V V mA mA mA mA mA mA mW C C
OFF(*) ON
Table 5: Recommended Operating Conditions
Parameter Value 1.65 to 4.3 0 to VCC 0 to 4.3 0 to VCC -55 to 125 VCC= 1.65V to 2.7V VCC= 3.0V to 4.3V 0 to 20 0 to 10 Unit V V V V C ns/V
Supply Voltage (note 1) Input Voltage Control Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time Control Input
1) Truth Table guaranteed: 1.2V to 4.3V.
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STG3684
Table 6: DC Specifications
Test Conditions Symbol Parameter VCC (V) TA = 25C Min. Typ. Max. Value -40 to 85C Min. 0.65VCC 1.4 1.4 1.5 1.7 2.2 0.40 0.50 0.50 0.50 0.50 1.3 0.50 0.50 0.50 0.80 3.0 3.0 0.40 0.50 0.50 0.50 0.50 1.3 0.50 0.60 0.60 0.80 4.0 4.0 Max. -55 to 125C Min. 0.65VCC 1.4 1.4 1.5 1.7 2.2 0.40 0.50 0.50 0.50 0.50 1.3 Max. Unit
VIH
VIL
RON
RON
RFLAT
High Level 1.65-1.95 0.65VCC Input Voltage 2.3-2.5 1.4 2.7-3.0 1.4 3.3 1.5 3.6 1.7 4.3 2.2 Low Level 1.65-1.95 Input Voltage 2.3-2.5 2.7-3.6 3.3 3.6 4.3 Switch ON 4.3 Resistance 3.0 (1) VS=0V to VCC 2.7 IS=100mA 2.3 1.8 1.65 ON Resistance VS=1.5V Match 2.7 IS=100mA between channels (1,2) ON 4.3 Resistance VS=1.5V 3.0 FLATNESS IS=100mA 2.7 (3) 2.3 1.65 VS=0.8V IS=100mA OFF State Leakage Current (nSn), (Dn) Input Leakage Current Quiescent Supply Current (1)
V
V
0.40 0.40 0.40 0.50 0.70 0.80
IOFF
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0.15
0.15
VS=0.3 or 4V
10
100
nA
VIN= 0 to 4.3V
0.1 0.05
1 0.2 1
A A
VIN=VCC or GND
Note 1: Guaranteed by design Note 2: RON = RON(MAX) - RON(MIN). Note 3: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges.
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STG3684
Table 7: AC Electrical Characteristics (CL = 35pF, R L = 50, tr = tf 5ns)
Test Condition Symbol Parameter VCC (V) 1.65-1.95 2.3-2.7 3.0-3.6 3.6-4.3 1.65-1.95 2.3-2.7 3.0-3.6 3.6-4.3 tOFF TURN-OFF time 1.65-1.95 2.3-2.7 3.0-3.6 3.6-4.3 Break Before Make Time Delay 1.65-1.95 2.3-2.7 3.0-3.6 3.6-4.3 1.65-1.95 2.3-2.7 3.0-3.6 3.6-4.3 TA = 25C Min. Typ. 0.45 0.40 0.30 0.30 70 30 30 30 45 25 25 25 2 2 2 15 15 15 50 40 35 35 30 30 30 40 40 40 50 50 50 60 60 60 ns Max. Value -40 to 85C Min. Max. -55 to 125C Min. Max. Unit
tPLH, tPHL Propagation Delay
VI=OPEN
ns
tON
TURN-ON time
VS=0.8V VS=1.5V VS=1.5V VS=1.5V VS=0.8V VS=1.5V VS=1.5V VS=1.5V CL=35pF RL= 50 VS=1.5V CL= 100pF RL= 1M VGEN= 0V RGEN= 0
tD
Q
Charge injection
Table 8: Analog Switch Characteristics (CL = 5pF, RL = 50, TA = 25C)
Test Condition Symbol Parameter VCC (V)
OIRR Xtalk THD
Off Isolation (1) Crosstalk
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BW CIN CSn CD
Total Harmonic Distortion
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pC
TA = 25C Typ. Max.
-40 to 85C Min. Max.
-55 to 125C Min. Max.
Unit
1.65-4.3 2.3-4.3
-3dB Bandwidth
1.65-4.3
VS= 1VRMS f= 100KHz VS= 1VRMS f= 100KHz RL= 600 VIN= 2VPP f= 20Hz to 20kHz RL= 50
dB dB
0.03 50 5
% MHz
Control Pin Input Capacitance Sn Port Capacitance D Port Capacitance when Switch is Enabled
3.3 3.3
f= 1MHz f= 1MHz
37 84
pF
Note 1: Off Isolation = 20Log10 (VD/VS), VD = output. VS = input at off switch
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STG3684
Figure 3: ON Resistance Figure 5: Bandwidth
Figure 4: OFF Leakage
Figure 6: Channel To Channel Crosstalk
OFF Isolation
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STG3684
Table 9: Test Circuit
CL = 5/35pF or equivalent (includes jig and probe capacitance) RL = 50 or equivalent RT = ZOUT of pulse generator (typically 50)
Figure 7: Break Before Make Time Delay
Figure 8: Charge Injection (VGEN=0V, RGEN=0, RL=1M, CL=100pF)
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STG3684
Table 10: Turn On, Turn Off Delay Time
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STG3684
QFN16 (3x3) MECHANICAL DATA
mm. DIM. MIN. A A1 A3 b D D2 E E2 e K L r 0.30 0.09 1.55 1.55 0.18 0.80 TYP 0.90 0.02 0.20 0.25 3.00 1.70 3.00 1.70 0.50 0.20 0.40 0.50 1.80 0.061 1.80 0.061 0.30 0.007 MAX. 1.00 0.05 MIN. 0.032 TYP. 0.035 0.001 0.008 0.010 0.118 0.067 0.118 0.067 0.012 MAX. 0.039 0.002 inch
E
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0.071 0.020
0.071
E2 K
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A3
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STG3684
Tape & Reel QFNxx/DFNxx (3x3) MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 3.3 3.3 1.1 4 8 12.8 20.2 60 18.4 0.130 0.130 0.043 TYP MAX. 330 13.2 0.504 0.795 2.362 0.724 MIN. TYP. MAX. 12.992 0.519 inch
0.157
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STG3684
Table 11: Revision History
Date 14-May-2004 01-Jun-2004 04-Jul-2005 Revision 2 3 4 Description of Changes Characteristics at VCC = 4.3 V Added on Tables 3, 4, 5, 6 and 7. ESD Performance (Analog Channels) added on top page. The Q Values on Table 6 has been updated.
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STG3684
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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